In some semiconductor buried contact applications upper 1 and lower 2 polycrystalline silicon layers form an electrical interconnect 3 to a substrate, see FIG. 1A. In the process for forming the electrical interconnect 3 polycrystalline silicon layer 1 is masked to define the electrical interconnect 3. Polysilicon 1, overlying polycrystalline silicon 2, and polycrystalline silicon 2 are etched to form the interconnect according to the mask. Typically a defect can occur along the horizontal interface between the upper 1 and lower 2 polycrystalline silicon layers. In one case the defect degrades the integrity of the electrical contact by preventing etching of the lower polycrystalline silicon layer in areas which are exposed during etching. This polycrystalline silicon which is not etched when intended can bridge between two poly interconnects thereby causing malfinctions in the part.
In one solution a single poly process is used, see FIG. 1B. In the single poly process a single layer of polycrystalline silicon is deposited and masked to form an electrical interconnect 4. However contamination problems occur at the poly/oxide interface during buried contact formation when the single poly process is used. In addition a required hydro-fluoric acid etch thins the gate oxide layer creating a non uniform gate oxide.
In addition when patterning a polycrystalline silicon above a buried contact region, trenching of the substrate and exposure of the buried contact region often occur due to misalignment. Thus a need exists to protect the buried contact from exposure and trenching during gate patterning. In one solution a buried contact cap is used to protect the buried contact region. However a parasitic transistor is formed around the contact cap thereby degrading the performance of the device. In one solution an implant mask has been added to lower contact resistance and eliminate parasitic transistor problems.
Thus a need exits for a method having minimal contamination when forming a polycrystalline silicon interconnect which has integrity within the contact without reflective notching. The method must also retain a conformal gate oxide layer without trenching or exposing the substrate.